As the global competition of semiconductor industry continues to become keen, semiconductor companies strive to maintain competitive advantages through the yield enhancement, the productivity improvement, and the cost reduction. Along with the shrinking of the feature size and the increasing complexity of the integrated circuit (IC) technology, the impact of unpredictable variations of manufacturing process are increasing and results in the low yield. The low yield problems can hardly be solved by the improvement and compensation of the manufacturing process. The modifications of the chip design also need to consider.
The chip size (i.e. die size), determined by the IC layout design, will be typically designed large enough to accommodate the micro-circuitry of ICs to ensure the desired functionality without considering wafer exposure effectiveness and efficiency. The wafer exposure effectiveness, the accounting of the gross dies per wafer is determined by the chip size and the exposure layout. In addition to the wafer exposure efficiency, the shot number of exposure equipment (i.e. stepper or scanner) for wafer exposure per layer is determined by the utilization of mask field which is also influenced by chip size.
In the conventional technologies, most studies focused on the yield improvement, but little studies made efforts on the improvements on the number of gross dies, the throughput, and the amount of exposure wafer per unit time in the lithography process. There are some existing studies that model the number of gross dies in terms of the chip size; however, they merely can be used as a try and error method to validate an improvement and will not do any favor for an IC designer to decide the designable variables.